library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity CONTATORE is
   port( CLOCK : in std_logic;
         RESET : in std_logic;
         Q     : out std_logic_vector(4 downto 0));
end CONTATORE;


architecture A of CONTATORE is

signal current_count, next_count : unsigned(4 downto 0);

begin
    -- registro del contatore
	process(RESET,CLOCK)
    begin
       if RESET = '1' then
         current_count <= conv_unsigned(0,5);
       elsif CLOCK'event and CLOCK='1' then
         current_count <= next_count;
       end if;
    end process;


    -- logica combinatoria per calcolo stato futuro
    next_count <= conv_unsigned(0,5) when current_count=conv_unsigned(23,5)   -- azzeramento contatore a fine conteggio
                                     else current_count+conv_unsigned(1,5);   -- incremento contatore

    Q <= conv_std_logic_vector(current_count,5);

end A;