-------------------------------------------------------------------------
-- adjust_button
--
-- Questo componente riduce ad una durata di un periodo di clock
-- i segnali corrispondenti alla pressione di un pulsante lunga a piacere
--------------------------------------------------------------------------

library IEEE;
   use IEEE.std_logic_1164.all;
   use IEEE.std_logic_arith.all;
   use IEEE.std_logic_unsigned.all;

entity adjust_button is
   port( clk    : in std_logic;
         reset  : in std_logic;
         button : in  std_logic;
         pulse  : out std_logic );
end adjust_button;

architecture A of adjust_button is
type stato is (s1, s2, s3, s4);
signal cs, ns : stato;
signal pulse_in : std_logic;

begin

   process(reset,clk)
   begin
      if reset='1' then 
            cs <= s1;
            pulse <= '0';
      elsif clk'event and clk='1' then
            cs <= ns;
            pulse <= pulse_in;
      end if;
   end process;


   process(cs, button)
   begin
      case cs is
         when s1 =>
              pulse_in <= button;
              if button='1' then 
                 ns <= s2;
              else
                 ns <= s1;
              end if;

         when s2 =>
              pulse_in <= '0';
              if button='1' then
                 ns <= s2;
              else
                 ns <= s3;
              end if;

         when s3 =>
              pulse_in <= button;
              if button='1' then
                 ns <= s4;
              else
                 ns <= s3;
              end if;

         when s4 =>
              pulse_in <= '0';
              if button='1' then
                 ns <= s4;
              else 
                 ns <= s1;
              end if;

         when others =>
              pulse <= '0';
              ns <= s1;
      end case;
  end process;

end A;


-------------------------------------------------

         
      


-----------------------------------------------------------------------
library IEEE;
   use IEEE.std_logic_1164.all;
   use IEEE.std_logic_arith.all;
   use IEEE.std_logic_unsigned.all;

entity OROLOGIO is
   port (
      MM     : out unsigned(5 downto 0);
      SS     : out unsigned(5 downto 0);
      CLOCK  : in std_logic;
      DEC_SEC : in std_logic;
      RESET  : in std_logic
   );
end OROLOGIO;

architecture C of OROLOGIO is
   signal MM_reg, SS_reg, next_MM, next_SS : unsigned(5 downto 0);
   signal DEC_MIN : std_logic;
begin

   process(CLOCK)
   begin
      if CLOCK'event and CLOCK='1' then
         if RESET = '1' then
            MM_reg <= conv_unsigned(2,6);
            SS_reg <= conv_unsigned(0,6);
         else
            MM_reg <= next_MM;
            SS_reg <= next_SS;
         end if;
      end if;
   end process;

   process(SS_reg, DEC_SEC)
   begin
      if DEC_SEC = '0' then
         next_SS <= SS_reg;
      elsif (SS_reg = conv_unsigned(0,6)) then
         next_SS <= conv_unsigned(59,6);
      else
         next_SS <= SS_reg - conv_unsigned(1,6);
      end if;
    end process;

   process(MM_reg, DEC_MIN)
   begin
      if DEC_MIN = '0' then
         next_MM <= MM_reg;
      elsif (MM_reg = conv_unsigned(0,6)) then
         next_MM <= conv_unsigned(2,6);
      else
         next_MM <= MM_reg - conv_unsigned(1,6);
      end if;
    end process;

  DEC_MIN <= '1' when (SS_reg = conv_unsigned(0,6) and DEC_SEC = '1') else '0';

MM <= MM_reg;
SS <= SS_reg;
  
end C;


---------------------

library IEEE;
   use IEEE.std_logic_1164.all;
   use IEEE.std_logic_arith.all;
   use IEEE.std_logic_unsigned.all;

entity TIMER is
   port (
      RESET : in std_logic;
      BUTTON : in std_logic;
      MM    : out unsigned(5 downto 0);
      SS    : out unsigned(5 downto 0);
      CLOCK : in std_logic;
      SOUND : out std_logic
   );
end TIMER;

architecture A of TIMER is
   component OROLOGIO
   port (
      MM     : out unsigned(5 downto 0);
      SS     : out unsigned(5 downto 0);
      CLOCK  : in std_logic;
      DEC_SEC : in std_logic;
      RESET  : in std_logic
   );
   end component;

  component clk_divider
  port ( clk   : in  std_logic;
         t1Hz : out std_logic;
         res   : in  std_logic);
  end component;


   type timer_state is ( stop, go, bell );
   signal present_state, next_state : timer_state;
   signal decrement_timer : std_logic;
   signal internal_MM, internal_SS : unsigned(5 downto 0);
   signal wave1Hz : std_logic;
   signal timeover : std_logic;
begin

   O0 : orologio port map(MM => internal_MM, SS => internal_SS, CLOCK => CLOCK, 
                          DEC_SEC => decrement_timer, RESET => RESET);

   CD0 : clk_divider port map (clk => CLOCK, t1Hz => wave1Hz, res => RESET );

   process(CLOCK)
   begin
      if CLOCK'event and CLOCK='1' then
         if RESET = '1' then
            present_state <= stop;
         else
            present_state <= next_state;
         end if;
      end if;
   end process;
   

   process(present_state, BUTTON, timeover, wave1Hz)
   begin

      case present_state is
         when stop =>
            decrement_timer <= '0';
            sound <= '0';
            
            if BUTTON = '1' then
               next_state <= go;
            else 
               next_state <= stop;
            end if;

          when go =>
             decrement_timer <= wave1Hz;
             sound <= '0';

             if timeover = '1' then
               next_state <= bell;
             elsif BUTTON = '1' then
                next_state <= stop;
             else
                next_state <= go;
             end if;

           when bell =>
              decrement_timer <= '0';
              sound <= '1';

              if BUTTON = '1' then
                 next_state <= stop;
              else next_state <= bell;
              end if;

           when others =>
               next_state <= stop;
               decrement_timer <= '0';
               sound <= '0';
       end case;
end process;

   timeover <= '1' when (internal_MM = conv_unsigned(0,6) and internal_SS = conv_unsigned(0,6)) else '0';

   MM <= internal_MM;
   SS <= internal_SS;

end A;


----------------------------


library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_arith.all;
  use IEEE.std_logic_unsigned.all;

entity clk_divider is
  port ( clk   : in  std_logic;
         t1Hz : out std_logic;
         res   : in  std_logic);
end clk_divider;

architecture A of clk_divider is
   signal count, new_count : unsigned(31 downto 0);
   signal reset_counter : std_logic;
   signal last_value : std_logic;
begin
  
   process(count)
   begin
      new_count <= count + conv_unsigned(1,32);
   end process;

   reset_counter <= res or last_value;

   process(clk)
   begin
      if clk'event and clk = '1' then
         if reset_counter = '1' then
            count <= conv_unsigned(0,32);
         else count <= new_count;
         end if;
      end if;
   end process;

   last_value <= '1' when count = conv_unsigned(26999999,32) else '0';
   --last_value <= '1' when count = conv_unsigned(2,32) else '0';
   t1Hz <= last_value;

end A;


-------------------------------------------------------------------------------
-- digit_to_7seg
-- 
-- Questo componente converte una cifra in formato BCD (0-9) nella
-- corrispondente configurazione di bit per il display 7 segmenti
-------------------------------------------------------------------------------

library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_arith.all;
  use IEEE.std_logic_unsigned.all;

entity digit_to_7seg is
  port( digit : in unsigned(3 downto 0);
        seg   : out std_logic_vector(6 downto 0) );
end digit_to_7seg;

architecture A of digit_to_7seg is
begin

   process(digit)
   begin
       case digit is 
          when conv_unsigned(0,4) => seg <= "1000000";
          when conv_unsigned(1,4) => seg <= "1111001";
          when conv_unsigned(2,4) => seg <= "0100100";
          when conv_unsigned(3,4) => seg <= "0110000";
          when conv_unsigned(4,4) => seg <= "0011001";
          when conv_unsigned(5,4) => seg <= "0010010";
          when conv_unsigned(6,4) => seg <= "0000010";
          when conv_unsigned(7,4) => seg <= "1111000";
          when conv_unsigned(8,4) => seg <= "0000000";
          when conv_unsigned(9,4) => seg <= "0010000";
          when others             => seg <= "0000110";
       end case;
   end process;


end A;

-----------------------------------------------------------------------------------


-----------------------------------------------------------------------------------
-- unsigned2digits
--
-- Questo componente converte un unsigned compreso tra 0 e 99 nelle due
-- cifre BCD corrispondenti
------------------------------------------------------------------------------------

library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_arith.all;
  use IEEE.std_logic_unsigned.all;

entity unsigned2digits is
   port( n : in unsigned(5 downto 0);
         u : out unsigned(3 downto 0);
         d : out unsigned(3 downto 0) );
end unsigned2digits;


architecture A of unsigned2digits is
begin   

   process(n)
   begin
      if n<conv_unsigned(10,6) then
         d <= conv_unsigned(0,4);
         u <= n(3 downto 0);
      elsif n<conv_unsigned(20,6) then
         d <= conv_unsigned(1,4);
         u <= conv_unsigned(n-conv_unsigned(10,6), 4);
      elsif n<conv_unsigned(30,6) then
         d <= conv_unsigned(2,4);
         u <= conv_unsigned(n-conv_unsigned(20,6), 4);
      elsif n<conv_unsigned(40,6) then
         d <= conv_unsigned(3,4);
         u <= conv_unsigned(n-conv_unsigned(30,6) ,4);
      elsif n<conv_unsigned(50,6) then
         d <= conv_unsigned(4,4);
         u <= conv_unsigned(n-conv_unsigned(40,6), 4);
      elsif n<conv_unsigned(60,6) then
         d <= conv_unsigned(5,4);
         u <= conv_unsigned(n-conv_unsigned(50,6), 4);
      elsif n<conv_unsigned(70,6) then
         d <= conv_unsigned(6,4);
         u <= conv_unsigned(n-conv_unsigned(60,6), 4);
      elsif n<conv_unsigned(80,6) then 
         d <= conv_unsigned(7,4);
         u <= conv_unsigned(n-conv_unsigned(70,6), 4);
      elsif n<conv_unsigned(90,6) then
         d <= conv_unsigned(8,4);
         u <= conv_unsigned(n-conv_unsigned(80,6), 4);
      else 
         d <= conv_unsigned(9,4);
         u <= conv_unsigned(n-conv_unsigned(90,6), 4);
      end if;

   end process;

end A;


----------------------------------------------------------------

library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_arith.all;



entity CII_timer_basket is
port(
		--------------------	Clock Input	 	--------------------	 
		--CLOCK_24  : in std_logic_vector(1 downto 0); --	24 MHz
		--CLOCK_27  : in std_logic_vector(1 downto 0); --	27 MHz
		--CLOCK_50  : in std_logic;					 --	50 MHz
		--EXT_CLOCK : in std_logic;					 --	External Clock
		
		--------------------	Push Button		--------------------
		--KEY : in std_logic_vector(3 downto 0);	--	Pushbutton[3:0]
		
		--------------------	DPDT Switch		--------------------
		-- SW : in std_logic_vector(9 downto 0);	--	Toggle Switch[9:0]
		
		--------------------	7-SEG Displa	--------------------
		--HEX0 : out std_logic_vector(6 downto 0);  --	Seven Segment Digit 0
		--HEX1 : out std_logic_vector(6 downto 0);  --	Seven Segment Digit 1
		--HEX2 : out std_logic_vector(6 downto 0);  --	Seven Segment Digit 2
		--HEX3 : out std_logic_vector(6 downto 0)  --	Seven Segment Digit 3
		
		------------------------	LED		------------------------
		--LEDG : out std_logic_vector(6 downto 0);	--	LED Green[7:0]
		--LEDR : out std_logic_vector(6 downto 0);	--	LED Red[9:0]
		
		------------------------	UART	------------------------
		--UART_TXD : out std_logic;			--	UART Transmitter
		--UART_RXD : out std_logic;			--	UART Receiver
		
		--------------------/	SDRAM Interface		----------------
		--DRAM_DQ    : inout std_logic_vector(15 downto 0);	--	SDRAM Data bus 16 Bits
		--DRAM_ADDR  : out std_logic_vector(11 downto 0);		--	SDRAM Address bus 12 Bits
		--DRAM_LDQM  : out std_logic;  						--	SDRAM Low-byte Data Mask 
		--DRAM_UDQM  : out std_logic;  						--	SDRAM High-byte Data Mask
		--DRAM_WE_N  : out std_logic;  						--	SDRAM Write Enable
		--DRAM_CAS_N : out std_logic;							--	SDRAM Column Address Strobe 
		--DRAM_RAS_N : out std_logic;							--	SDRAM Row Address Strobe
		--DRAM_CS_N  : out std_logic;							--	SDRAM Chip Select
		--DRAM_BA_0  : out std_logic;							--	SDRAM Bank Address 0
		--DRAM_BA_1  : out std_logic;							--	SDRAM Bank Address 0
		--DRAM_CLK   : out std_logic;							--	SDRAM Clock
		--DRAM_CKE   : out std_logic;							--	SDRAM Clock Enable
		
		--------------------	Flash Interface		----------------
		--FL_DQ    : inout std_logic_vector(7 downto 0);	--	FLASH Data bus 8 Bits
		--FL_ADDR  : out std_logic_vector(21 downto 0);	--	FLASH Address bus 22 Bits
		--FL_WE_N  : out std_logic;						--	FLASH Write Enable
		--FL_RST_N : out std_logic;						--	FLASH Reset
		--FL_OE_N  : out std_logic;						--	FLASH Output Enable
		--FL_CE_N  : out std_logic; 						--	FLASH Chip Enable
		
		--------------------	SRAM Interface		----------------
		--SRAM_DQ   : inout std_logic_vector(15 downto 0);	--	SRAM Data bus 16 Bits
		--SRAM_ADDR : out std_logic_vector(17 downto 0);		--	SRAM Address bus 18 Bits
		--SRAM_UB_N : out std_logic;							--	SRAM High-byte Data Mask 
		--SRAM_LB_N : out std_logic;							--	SRAM Low-byte Data Mask 
		--SRAM_WE_N : out std_logic;							--	SRAM Write Enable
		--SRAM_CE_N : out std_logic;							--	SRAM Chip Enable
		--SRAM_OE_N : out std_logic;							--	SRAM Output Enable
		
		--------------------	SD_Card Interface	----------------
		--SD_DAT  : inout std_logic;							--	SD Card Data
		--SD_DAT3 : inout std_logic;							--	SD Card Data 3
		--SD_CMD  : inout std_logic;							--	SD Card Command Signal
		--SD_CLK	: inout std_logic;							--	SD Card Clock
		
		--------------------	USB JTAG link	--------------------
		--TDI : in std_logic;				-- CPLD -> FPGA (data in)
		--TCK : in std_logic; 			-- CPLD -> FPGA (clk)
		--TCS : in std_logic; 			-- CPLD -> FPGA (CS)
	    --TDO : out std_logic;			-- FPGA -> CPLD (data out)
	
		--------------------	I2C		----------------------------
		--I2C_SDAT : inout std_logic;		--	I2C Data
		--I2C_SCLK : out std_logic;		--	I2C Clock
		
		--------------------	PS2		----------------------------
		--PS2_DAT : in std_logic;			--	PS2 Data
		--PS2_CLK : in std_logic;			--	PS2 Clock
		
		--------------------	VGA		----------------------------
		--VGA_HS : out std_logic;						--	VGA H_SYNC
		--VGA_VS : out std_logic;						--	VGA V_SYNC
		--VGA_R  : out std_logic_vector(3 downto 0)	--	VGA Red[3:0]
		--VGA_G  : out std_logic_vector(3 downto 0)	--	VGA Green[3:0]
		--VGA_B  : out std_logic_vector(3 downto 0)	--	VGA Blue[3:0]
		
		----------------	Audio CODEC		------------------------
		--AUD_ADCLRCK : out std_logic;		--	Audio CODEC ADC LR Clock
		--AUD_ADCDAT  : in std_logic;		--	Audio CODEC ADC Data
		--AUD_DACLRCK : out std_logic;		--	Audio CODEC DAC LR Clock
		--AUD_DACDAT  : out std_logic;		--	Audio CODEC DAC Data
		--AUD_BCLK    : in std_logic;		    --	Audio CODEC Bit-Stream Clock
		--AUD_XCK     : out std_logic;		--	Audio CODEC Chip Clock
		
		--------------------	GPIO	----------------------------
		--GPIO_0 : inout std_logic_vector(35 downto 0);	--	GPIO Connection 0
		--GPIO_1 : inout std_logic_vector(35 downto 0)	--	GPIO Connection 1
		
        CLOCK_27  : in std_logic_vector(1 downto 0); -- 27 MHz
		KEY : in std_logic_vector(3 downto 0);       -- Pushbutton[3:0]
		HEX0 : out std_logic_vector(6 downto 0);     -- Seven Segment Digit 0
		HEX1 : out std_logic_vector(6 downto 0);     -- Seven Segment Digit 1
		HEX2 : out std_logic_vector(6 downto 0);     -- Seven Segment Digit 2
		HEX3 : out std_logic_vector(6 downto 0)      -- Seven Segment Digit 3		
	);
end CII_timer_basket;




architecture A of CII_timer_basket is

component adjust_button is
   port( clk    : in std_logic;
         reset  : in std_logic;
         button : in  std_logic;
         pulse  : out std_logic );
end component;


component TIMER is
   port (
      RESET  : in std_logic;
      BUTTON : in std_logic;
      MM     : out unsigned(5 downto 0);
      SS     : out unsigned(5 downto 0);
      CLOCK  : in std_logic;
      SOUND  : out std_logic
   );
end component;

component unsigned2digits is
   port( n : in unsigned(5 downto 0);
         u : out unsigned(3 downto 0);
         d : out unsigned(3 downto 0) );
end component;

component digit_to_7seg is
  port( digit : in unsigned(3 downto 0);
        seg   : out std_logic_vector(6 downto 0) );
end component;


signal ck : std_logic;
signal my_key, my_key_1cycle : std_logic;
signal my_reset : std_logic;

signal sec, min   : unsigned(5 downto 0);
signal sec_u, sec_d, min_u, min_d :  unsigned(3 downto 0);


attribute syn_keep : boolean;
attribute noprune  : boolean;
attribute syn_preserve : boolean;


attribute syn_keep of sec : signal is true;
attribute noprune  of sec : signal is true;
attribute syn_keep of min : signal is true;
attribute noprune  of min : signal is true;

attribute syn_keep of sec_u : signal is true;
attribute noprune  of sec_u : signal is true;
attribute syn_keep of sec_d : signal is true;
attribute noprune  of sec_d : signal is true;

attribute syn_keep of min_u : signal is true;
attribute noprune  of min_u : signal is true;
attribute syn_keep of min_d : signal is true;
attribute noprune  of min_d : signal is true;

attribute syn_keep of my_key_1cycle : signal is true;
attribute noprune  of my_key_1cycle : signal is true;
attribute syn_preserve of my_key_1cycle : signal is true;



begin

   -- associo i pin della development board a dei segnali interni di nome
   -- e tipo pił appropriati
   my_key   <= not KEY(0);  -- i tasti sono attivi bassi
   my_reset <= not KEY(3);
   ck       <= CLOCK_27(0);


   -- instanzio un componente che riduce le pressioni del pulsante di ingresso a un ciclo
   -- di clock di durata
   adjb0: adjust_button port map(clk => ck, reset => my_reset, button => my_key, pulse => my_key_1cycle);


   -- istanzio come componente la soluzione dell'esercizio
   timer0: timer port map(RESET=>my_reset, CLOCK=>ck, BUTTON=>my_key_1cycle, MM=>min, SS=>sec);



   -- creo la rete di interfaccia tra il componente timer e i dispositivi
   -- presenti sulla development board
   u0: unsigned2digits port map( n => sec, u => sec_u, d =>sec_d );
   u1: unsigned2digits port map( n => min, u => min_u, d =>min_d );

   d0: digit_to_7seg port map( digit => sec_u, seg => HEX0 );
   d1: digit_to_7seg port map( digit => sec_d, seg => HEX1 );
   d2: digit_to_7seg port map( digit => min_u, seg => HEX2 );
   d3: digit_to_7seg port map( digit => min_d, seg => HEX3 );
   

end A;