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CACD Group
updated 2000.03.30
Author Arpad Buermen

XSPICE Extensions

SPICE OPUS includes XSPICE extensions to SPICE3 since version 1.3 along with the code model libraries provided by Georgia Tech Research Institute.
  1. Overview
  2. Introduction to Using Code Models in Circuits
  3. Selecting How SPICE OPUS Expands Subcircuits
  4. Digital nodes
  5. .cm library files included with SPICE OPUS
  6. How to build your own .cm library

What is XSPICE

XSPICE is a group of extensions to the SPICE3 simulator developed by the Georgia Tech Research Institute (GTRI). It enables you to:
  • Perform simulation of event-driven and mixed-mode circuits.
    Mixed mode simulation is not limited to simulation of interconnected digital and analog circuits. It can simulate any kind of mixed-mode discrete-time/analog system. Discrete time signals can have more than 2 or 3 values (HI, LO and UNKNOWN) This depends on the type of the node whose value is the value of the signal. Beside digital, you can also have real (for simulation of floating-point DSP algorithms) or integer nodes (for simulation for fixed-point DSP algorithms). Of course various signal types can be converted among each other by using node bridges.
  • Add new discrete time node types that can be loaded at runtime (1, 2)
    User Defined Nodes or UDNs - e.g. digital or real nodes
  • Add new devices to SPICE (Code Models or CMs) that can be loaded at runtime. (1, 2)
    These devices can be either analog (e.g. Laplace s-domain block), event-driven (e.g. digital nand gate, z-domain delay) or hybrid (e.g. controlled digital oscillator, digital to analog node bridge)
  • Digital nodes.
    A 3-state 4-strength digital node (UDN) is built-in into the simulator. An extensive code model .cm library is provided with SPICE OPUS for simulating digital circuits.
  • Subcircuit expansion is now more intuitive and accessing internal nodes, devices and models of a subcircuit is now easier for the user.
  • Dependent polynomial source support (SPICE 2g6) is included. The parser translates the SPICE2g6 syntax to a code model description of the source. This code model then simulates the source. (2)
  • SIN, PULSE and SFFM transient sources now support an additional phase parameter. SFFM has now 2 phase parameters (for carrier and modulation).
  • Capacitor an inductor code models that support initial conditions and supply ramping are included.
  • Supply ramping for transient analysis is provided.
    At startup values for all independent current and voltage sources and initial conditions for capacitor and inductor code models are linearely ramped towards their final value at a rate which you define.
  • Matrix conditioning.
    In case there is no DC path to the ground you can instruct the simulator to add a resistor with high resistance connected to ground at each node. This is of course the faster solution to the problem. But the better one is still the classical one: finding why the node has no path to ground and fixing the circuit appropriately.
  • Gmin stepping and source stepping algorithms can be disabled separately. Improved control over DC analysis algorithms and mixed mode simulation is provided.
  • Improved convergence problem reporting.
(*) Requires knowledge of C programming. Supported under Windows, Linux and Solaris.
(**) Circuits containing CMs support AC, DC and transient analyses. AC analysis is not supported for circuits with event-driven nodes.

General enhancements

Code models
XSPICE extends the basic SPICE functionality with code models (CMs). Code models are device models written in C and can be dynamically loaded into the simulator core. CMs can support the following analyses: OP, DC, TRAN and AC. CMs are not limited to analog models but can be purely event-driven (digital and gate) or hybrid (controlled digital oscillator or node bridges, e.g. analog-to-digital node bridge).

Event-driven simulation
In case your circuits contain no event-driven nodes (UDNs) nor event-driven code model instances (pure event-driven and hybrid CM instances) the event-driven simulator doesn't participate in the simulation and everything is done by the analog simulator.
Mixed mode simulation is used when your circuit contanins at least one event-driven CM instance. Event-driven algorithms work together with the analog simulator to produce results. Supported analyses for mixed-mode simulation are OP, DC and TRAN. Mixed-mode simulation and analog simulation are iteratively exchanged until event-driven outputs of event-driven CM instances stop changing.
Mixed mode simulation is implemented as "native mode". This means that the event driven simulator is implemented in the same executable as the analog simulator thus eliminating unneccesary overhad caused by the communication between both simulators that is typical of "glued mode" implementations.
In order to perform mixed-mode simulation you must have at least one mixed-mode CM instance in your circuit. Event-driven instances connect with their event-driven ports (inputs and outputs) to event-driven nodes. These nodes differ from analog nodes. They are implemented as User Defined Nodes (UDNs). UDNs can change their value only at discrete times. There can be many different UDNs in your circuit. A distinct UDN type has a predefined set of values. For instance a digital UDN (digital UDN is built-in into the simulator core) can have one of 3 logic levels combined with one of 4 logic strengths. The code that describes a certain UDN defines the way multiple conflicting outputs of different CM ports that are connected to the same UDN are resolved in order to produce the value for the UDN. Users can write their own UDNs in C and dynamically load them into the simulator core.
To connect the analog part of the circuit and the digital part of the circuit special hybrid CMs are used. These CMs are called node bridges. They translate one node type value into some other node type. For example to translate an analog node value into digital node value an analog-to-digital CM instance is used. For inverse translation you can use the digital-to-analog CM.

SPICE2g6 POLY sources
XSPICE supports SPICE2g6 polynomial controlled sources (POLY sources). They are impelemnted as CMs. You don't have to use the standard CM approach to adding a CM instance to your circuit. The translation from the SPICE2g6 syntax into XSPICE syntax is handled by the parser when the circuit is loaded. Polynomial source CM is built-in into the simulator core.
Polynomial source type Syntax
VCVS Ename N+ N- (POLY (ND)) NC1+ NC1- .. NCND+ NCND- P0 (P1 ...)
CCCS Fname N+ N- (POLY (ND)) Vname1 .. VnameND P0 (P1 ...)
VCCS Gname N+ N- (POLY (ND)) NC1+ NC1- .. NCND+ NCND- P0 (P1 ...)
CCVS Hname N+ N- (POLY (ND)) Vname1 .. VnameND P0 (P1 ...)
In case ND=1 (one dimensional POLY source) POLY(1) may be ommited.

Arbitrary phase sources
Arbitrary phase is supported for the following transient sources: SIN, PULSE and SFFM:
Transient source Syntax
PULSE PULSE (Vlevel1, Vlevel2, Delay, Rise_Time, Fall_Time, Pulse_Width, Period, Phase)
SIN SIN (Voffset Vamplitude Frequency Delay_Time Damping_Coeff Phase)
SFFM SFFM (Voffset Vamplitude Carrier_Frequency Modulation_Index Signal_Frequency Carrier_Phase Signal_Phase)

Capacitor and inductor CMs
These CMs support initial conditions and supply ramping. 

  A1 1 0 cmodel
  .MODEL cmodel capacitor(c=1000u ic=1)
  
  A2 1 0 lmodel
  .MODEL lmodel inductor(l=1m ic=0.05)

Supply ramping
Supply ramping is provided as an option to a transient analysis to simulate the turn on of power supplies. The values of all independent sources and initial conditions for capacitor and inductor CMs are ramped from 0 toward their final values in a time specified by user. To turn on the supply ramping option, use: 

  .options ramptime=RAMPING_TIME_IN_SECONDS

Matrix conditioning
In case an analog node has no DC path to the ground, the simulation doesn't converge and you get an error message. In order to make the circuit work you must find the node and provide a DC path to the ground (in most cases you would add a very large resistance between the problematic node and the ground node). XSPICE has the 'rshunt' option which does this for every analog node in the circuit. To turn on this option, use: 

  .options rshunt=RSHUNT_VALUE
You can use for example 1.0e12 for the rshunt value. In case you still have problems, try decresing the rshunt value gradualy to 1.0e9 or less. The best solution to the 'No DC path to the ground.' is still to find the node that is causing the problems and add only one 'rshunt' resistor manually to that node.

DC convergence options
The default convergence problem solving algorithm for DC analyses is GMIN stepping. If GMIN stepping fails, source stepping is used. In order to make the source stepping the default algorithm, set the gminsteps option to 0: 

  .options gminsteps=0
  .options srcsteps=1000
This makes source stepping the default convergence problem solving algorithm. After 1000 source stepping steps the GMIN stepping is used.
The 'maxopalter' option sets the maximum number of analog/event alternations. To set the maximum number of event iterations, use the 'maxevtiter' option. 
  .options maxopalter=1000
  .options maxevtiter=2000
In order to enable the analog/event alternations, use: 
  .options noopalter=FALSE
To set relative and absolute step size limits applied to CM inputs in solving for the DC operating point: 
  .options convstep=0.01
  .options convabsstep=1e-6

Code models, UDNs and .cm files

SPICE has a built-in set of device models (diode, BJT, MOS, ...) that can be used in your circuits. XSPICE enables you to create your own device models and use them in your circuits. You can write such a model (CM) in C.
Since XSPICE has an event-driven simulator built-in that is capable of simulating event driven circuits you can define your own event-driven node types. A digital node is built-in into the SPICE OPUS simulator but you can create also other event-driven node types. These node types are User Defined Node types (UDNs) and are also written in C.
In order to use the CMs and UDNs written in C in your circuits you must compile them and then load them into the simulator before loading your circuit that uses these CMs and UDNs. SPICE OPUS comes with a precompiled set of CMs and UDNs. Among those you can find integer and real UDNs, blocks for system level analog simulation, various digital gates and node bridges.

CMs and UDNs are stored in a .cm file that can be loaded into the simulator. In order to load a .cm file, type the following command in the NUTMEG prompt: 

  cmload filename.cm
Example: 
  Spice Opus 2 -> cmload analog.cm
  analog.cm, version 1.0, Feb 25 2000
  Analog system-level simulation library.
  Author: GTRI, adapted by Arpad Buermen
  Copyright: (c)2000 CACD Group, FE Ljubljana
  Found 17 CM device(s) and 0 UDN(s).
  Successfully loaded 17 CM device(s) and 0 UDN(s).
cmload searches for the .cm file in the SPICE lib/cm directory, in the system dll search path and in the current directory. The supplied .cm libraries are loaded at SPICE OPUS startup. The command that load these .cm files are in the spinit script provided with SPICE OPUS (lib/scripts): 
  cmload analog.cm
  cmload digital.cm
  cmload xtradev.cm
  cmload xtraevt.cm
To see which analyses, UDNs and CMs are available at the moment use the siminfo command: 
  siminfo [analyses] [devices] [nodes] [all]

  siminfo all
shows all simulator information.

Compiled CMs and UDNs are linked together with some header information and functions into a .cm file. A .cm file is actually a dll containing the compiled CMs and UDNs. Templates for creating .cm files are in the template/ directory. This directory contains template files for describing CMs and UDNs, .cm header .h and .c files and makefiles for Microsoft Visual C++ and Linux/Solaris GCC that build the .cm files containing your CMs and UDNs.

Supported Analyses

As already mentioned XSPICE CMs can support DC, AC and transient analyses. SPICE OPUS supports all SPICE3 analyses for pure analog circuits without CMs. For pure analog circuits with one or more CMs SPICE OPUS supports OP, DC, AC and TRAN analyses. For mixed-mode circuits SPICE OPUS supports only OP, DC and TRAN analyses.
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