updated 2000.03.30
Author Janez Puhan
Four Phase Ring Counter
Cascading two D flip-flops and connecting the inverting output of the last to the D input of the first, results in a two bit ring counter. Binary signals are stored and shifted alternately resulting in four square wave outputs phased 90° apart. Both of the following examples lead to the same result. The first one uses linear polynomial gates with limiting transistor inverters and the second uses CMOS gates. Comparing these two concepts provides information about the cost of using polynomials versus MOSFETs in terms of memory and simulation runtime.
Polynomial gates
The input file
four phase ring counter 1
.ic v(2)=0 v(3)=1V v(4)=0 v(5)=1V
.control
tran 0.1us 10us
plot v(1)+2 v(2) v(3)-2 v(4)-4 xlabel t[s] ylabel 'v(1) v(2) v(3) v(4) [V]'
+ title 'TRAN analsis'
.endc
v1 1 0 dc 0 pulse 0 1V 1us 0 0 1us 2us
r1 1 0 1g
b1 10 0 v = v(1) * v(5)
b2 11 0 v = v(1) * v(6)
b3 12 0 v = v(3) * v(6)
b4 13 0 v = v(2) * v(7)
b5 14 0 v = v(1) + v(2) - v(1) * v(2)
b6 15 0 v = v(1) + v(8) - v(1) * v(8)
b7 16 0 v = v(5) + v(8) - v(5) * v(8)
b8 17 0 v = v(4) + v(9) - v(4) * v(9)
x1 10 6 inv
x2 11 7 inv
x3 12 2 inv
x4 13 3 inv
x5 14 8 inv
x6 15 9 inv
x7 16 4 inv
x8 17 5 inv
.subckt inv 1 2
v0 3 0 dc 1V
q1 2 1 3 noname1
q2 2 1 0 noname2
.model noname1 pnp rb=1 cjc=1nF
.model noname2 npn rb=1 cjc=1nF
.ends
.end
The results
CMOS gates
The input file
four phase ring counter 2
.control
tran 0.1us 10us
plot v(1)+20 v(2) v(3)-20 v(4)-40 xlabel t[s] ylabel 'v(1) v(2) v(3) v(4) [V]'
+ title 'TRAN analsis'
.endc
v1 1 0 dc 0 pulse 0 15V 2us 0 0 1us 2us
x1 1 5 6 nand
x2 1 6 7 nand
x3 3 6 2 nand
x4 7 2 3 nand
x5 2 1 8 nor
x6 8 1 9 nor
x7 8 5 4 nor
x8 4 9 5 nor
.subckt nand 1 2 3
v1 4 0 dc 0 pulse 0 15V
c1 1 0 5pF
c2 2 0 5pF
m1 3 1 4 4 noname1
m2 3 2 4 4 noname1
m3 5 1 0 0 noname2
m4 3 2 5 5 noname2
.model noname1 pmos
.model noname2 nmos
.ends
.subckt nor 1 2 3
v1 7 0 dc 0 pulse 0 15V
c1 1 0 5pF
c2 2 0 5pF
m1 4 1 7 7 noname1
m2 3 2 4 4 noname1
m3 3 2 0 0 noname2
m4 3 1 0 0 noname2
.model noname1 pmos
.model noname2 nmos
.ends
.end
The results
