Exclusive OR Gate

The circuit

As indicated in the previous case, higher level subcircuits may be set up by using a hierarchy of lower level subcircuits. In this example, an exclusive-or gate is built up with four NAND gates. As a result, a high output appears if only one single input is high. If both inputs are zero or high simultaneously, the output remains at zero. The ability to deliver an output signal with uneven inputs can be utilised for edge detection of binary signals. When both inputs are tied together, the signal in one path is delayed by a resistor and the input gate capacitance. In the vicinity of the input pulse edges, a momentary inequality of the input values occurs, producing an output pulse two times each period.

The input file

exclusive or gate

.control
tran 50ns 10us
plot v(1)+60 v(2)+40 v(3)+20 v(4) v(5)-20 v(6)-40 xlabel t[s]
  + ylabel 'v(1) v(2) v(3) v(4) v(5) v(6) [V]' title 'TRAN analysis'
.endc

v1 1 0 dc 0 pulse 0 15V 1us 0 0 3us 6us

r1 1 2 30k

x1 2 1 3 nand2mos
x2 3 1 4 nand2mos
x3 2 3 5 nand2mos
x4 5 4 6 nand2mos

.subckt nand2mos 1 2 3
v1 4 0 dc 15V

c1 1 0 5pF
c2 2 0 5pF

m1 3 1 4 4 noname1
m2 3 2 4 4 noname1
m3 5 1 0 0 noname2
m4 3 2 5 5 noname2

.model noname1 pmos
.model noname2 nmos
.ends

.end

The results