library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity controllore is
	port (
		CLK 		: in std_logic;
		RESET 		: in std_logic;
		--INTERFACCIA SENSORE
		READ_DATA 	: out std_logic;
		DATA_READY 	: in std_logic;
		SENSOR_DATA : in unsigned(7 downto 0);
		--INTERFACCIA MEMORIA FLASH
		FLASH_ADDR 	: out std_logic;
		FLASH_DATA 	: in unsigned(7 downto 0);
		--INTERFACCIA PANNELLO DI CONTROLLO
		READ_TEMP 	: in std_logic;
		SERIAL_DATA : out std_logic;
		STOP 		: out std_logic;
		SERIAL_CLOCK: out std_logic);
end controllore;
		
architecture behavioural of controllore is

type state is (idle, read_offset, wait_offset, sample_offset, read_scale, wait_scale, sample_scale, read_sensor, wait_sensor, sample_sensor, scaling, transmission);
signal next_state, current_state : state;
signal start_cnt_5, stop_cnt_5 : std_logic;
signal start_cnt_9, stop_cnt_9 : std_logic;
signal enable_offset, enable_scale, enable_data, enable_temperature : std_logic;
signal current_cnt_5, next_cnt_5 : unsigned (2 downto 0);
signal current_cnt_9, next_cnt_9 : unsigned (3 downto 0);
signal register_offset, register_scale, register_data : unsigned (7 downto 0);
signal temperature : unsigned (8 downto 0);
	
begin

	--comb
	process(current_state, read_temp, stop_cnt_5, data_ready, stop_cnt_9) is
		begin
		
		flash_addr <= 'Z';
		start_cnt_5 <= '0';
		start_cnt_9 <= '0';
		enable_offset <= '0';
		enable_scale <= '0';
		enable_data <= '0';
		enable_temperature <= '0';
		read_data <= '0';
		
		case current_state is
			
			when idle =>
				if read_temp = '1' then
					next_state 	<= read_offset;
				else
					next_state 	<= idle;
				end if;
			
			when read_offset =>
				flash_addr 		<= '0';
				next_state 		<= wait_offset;
			
			when wait_offset 	=>
				flash_addr 		<= '0';
				start_cnt_5 	<= '1';
				if stop_cnt_5 = '1' then
					next_state 	<= sample_offset;
				else
					next_state 	<= current_state;
				end if;
				
			when sample_offset 	=>
				flash_addr 		<= '0';
				enable_offset 	<= '1';
				next_state 		<= read_scale;
				
			when read_scale 	=>
				flash_addr 		<= '1';
				next_state 		<= wait_scale;
				
			when wait_scale 	=>
				flash_addr 		<= '1';
				start_cnt_5 	<= '1';
				if stop_cnt_5 = '1' then
					next_state 	<= sample_scale;
				else
					next_state 	<= current_state;
				end if;
				
			when sample_scale 	=>
				flash_addr 		<= '1';
				enable_scale 	<= '1';
				next_state 		<= read_sensor;
				
			when read_sensor 	=>
				READ_DATA 		<= '1';
				next_state 		<= wait_sensor;
				
			when wait_sensor =>
				if DATA_READY = '1' then 
					next_state <= sample_sensor;
				else
					next_state <= current_state;
				end if;
				
			when sample_sensor =>
				enable_data 		<= '1';
				next_state <= scaling;
				
			when scaling =>
				enable_temperature 	<= '1';
				next_state 			<= transmission;
			
			when transmission =>
				start_cnt_9 <= '1'; 
				if stop_cnt_9 = '1' then
					next_state <= idle;
				else
					next_state <= current_state;
				end if;
				
			when others =>
			next_state <= idle;
		
		end case;
		
	end process;
	
	--count5
	process(reset, clk)
		begin
			if reset = '1' then
				current_cnt_5 <= conv_unsigned(0,3);
			elsif(clk = '1' and clk' event) then
				if (start_cnt_5 = '1') then
					current_cnt_5 <= next_cnt_5;
				end if;
			end if;
		end process;
		
	stop_cnt_5 <= '1' when current_cnt_5 = conv_unsigned(5,3) else '0';
	
	next_cnt_5 <= conv_unsigned(0,3) when stop_cnt_5 = '1' else
				current_cnt_5+conv_unsigned(1,3);
	
	--count9
	process(reset, clk)
		begin
			if reset = '1' then
				current_cnt_9 <= conv_unsigned(0,4);
			elsif(clk = '1' and clk' event) then
				if (start_cnt_9 = '1') then
					current_cnt_9 <= next_cnt_9;
				end if;
			end if;
		end process;
	
	stop_cnt_9 <= '1' when current_cnt_9 = conv_unsigned(9,4) else '0';
	
	next_cnt_9 <= conv_unsigned(0,4) when stop_cnt_9 = '1' else
				current_cnt_9+conv_unsigned(1,4);	
	
	stop <= stop_cnt_9;
	
	process(clk, current_cnt_9, temperature)
	begin
		case current_cnt_9 is
			
			when conv_unsigned(0,4) =>
				serial_data <= temperature(0);
			when conv_unsigned(1,4) =>
				serial_data <= temperature(1);
			when conv_unsigned(2,4) =>
				serial_data <= temperature(2);
			when conv_unsigned(3,4) =>
				serial_data <= temperature(3);
			when conv_unsigned(4,4) =>
				serial_data <= temperature(4);
			when conv_unsigned(5,4) =>
				serial_data <= temperature(5);
			when conv_unsigned(6,4) =>
				serial_data <= temperature(6);
			when conv_unsigned(7,4) =>
				serial_data <= temperature(7);
			when conv_unsigned(8,4) =>
				serial_data <= temperature(8);
			when others =>
			    serial_data <= '0';
			
		end case;
	end process;
	
	serial_clock <= clk when start_cnt_9 = '1' else '0';
	
	--register_offset
	reg_off: process(reset, clk) is
		begin
		if reset = '1' then 
			register_offset <= conv_unsigned(0,8);
		elsif(clk = '1' and clk' event) then
			if enable_offset = '1' then
				register_offset <= flash_data;
			end if;
		end if;
	end process reg_off;
	
	--register_scale
	reg_scale: process(reset, clk) is
		begin
		if reset = '1' then 
			register_scale <= conv_unsigned(0,8);
		elsif(clk = '1' and clk' event) then
			if enable_scale = '1' then
				register_scale <= flash_data;
			end if;
		end if;
	end process reg_scale;
	
	--register_data
	reg_data: process(reset, clk) is
		begin
		if reset = '1' then 
			register_data <= conv_unsigned(0,8);
		elsif(clk = '1' and clk' event) then
			if enable_data = '1' then
				register_data <= sensor_data;
			end if;
		end if;
	end process reg_data;
	
	--register_temperature
	reg_temp: process(reset, clk) is
		begin
		if reset = '1' then
			temperature <= conv_unsigned(0,9);
		elsif(clk = '1' and clk' event) then
			if enable_temperature = '1' then
				temperature <= conv_unsigned((("0000" & register_data(7 downto 4))+ register_offset)*register_scale,9);
			end if;
		end if;
	end process reg_temp;
	
	--parte sequenziale
	seq: process (reset, clk, next_state) is
		begin
		if reset = '1' then 
			current_state <= idle;
		elsif(clk = '1' and clk' event) then
			current_state <= next_state;
		end if;
	end process seq;
	
end architecture behavioural;