library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity CounterWithLoad is
  generic(
    counter_width       : natural := 32);
  port(
    CLK                 : in  std_logic;
    RESET               : in  std_logic;
    Enable              : in  std_logic;
    Load_comando        : in  std_logic;
    Load_valore         : in  unsigned(counter_width-1 downto 0);
    VALORE              : out unsigned(counter_width-1 downto 0));
end CounterWithLoad;

architecture A of CounterWithLoad is
  
  signal next_value, value_temp : unsigned(counter_width-1 downto 0);
  
begin
  
  process(CLK)
  begin
    if CLK'event and CLK='1' then
      if RESET='1' then
        value_temp<= conv_unsigned(0,counter_width);
      elsif Load_comando = '1' then
        value_temp <= Load_valore;
      elsif Enable='1' then
        value_temp<= next_value;
      end if;
    end if;
  end process;
  
  next_value      <= value_temp-conv_unsigned(1,counter_width);
  VALORE          <= value_temp;
  
end A;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity CONTROLLORE is
  port(
    CLK      : in std_logic;
    Reset    : in std_logic;
     
    START    : in std_logic;
    STOP     : in std_logic;
    GOAL     : in std_logic;
    
    MIN      : out unsigned(4 downto 0);
    SEC      : out unsigned(5 downto 0);
    
    TEMPO    : out unsigned(1 downto 0);
    SIRENA   : out std_logic);
end CONTROLLORE;   

architecture Esercizio of CONTROLLORE is
  
  type stato is (Idle, CARICA, CONTA,FERMA,sirena_attiva, incrementa);
  signal current_state,next_state	:stato;
  
  signal enable_cont_sec                : std_logic;
  signal load                           : std_logic;
  signal enable_cont_min                : std_logic;
  
  signal cont_sec                       : unsigned(5 downto 0);    
  signal cont_min                       : unsigned(4 downto 0);
  signal cont_secondo                   : unsigned(13 downto 0);
  signal unminuto, fineminuti,unsecondo : std_logic;
  
  component CounterWithLoad
    generic(
      counter_width     : natural := 32);
    port(
      CLK               : in  std_logic;
      RESET             : in  std_logic;
      Enable            : in  std_logic;
      Load_comando      : in  std_logic;
      Load_valore       : in  unsigned(counter_width-1 downto 0);
      VALORE            : out unsigned(counter_width-1 downto 0));
  end component;
  
--seconda parte SEGNALI
  
  signal current_conta_tempo, next_conta_tempo  : unsigned(1 downto 0);
  signal current_sirena, next_sirena 	        : unsigned(12 downto 0);
  signal incrementa_tempo 			: std_logic;
  signal attiva_sirena 				: std_logic;
  signal end_sirena 				: std_logic;
  
begin
  
  ContaMinuti : CounterWithLoad
    generic map (
      counter_width   	=> 5)
    port map (
      CLK               => CLK,
      RESET             => RESET,
      Enable            => enable_cont_sec and unminuto,
      Load_comando      => load,
--  Load_valore         => conv_unsigned(19,5),
      Load_valore       => conv_unsigned(2,5),
      Valore            => cont_min);
  
  ContaSecondo : CounterWithLoad
    generic map (
      counter_width     => 14)
    port map (
      CLK 		=> CLK,
      RESET 		=> RESET,
      Enable		=> enable_cont_sec,
      Load_comando      => load or unsecondo,
--   Load_valore        => conv_unsigned(9999,14),
      Load_valore 	=> conv_unsigned(3,14),
      Valore		=> cont_secondo);
  
  ContaSecondi : CounterWithLoad
    generic map (
      counter_width     => 6)
    port map (
      CLK               => CLK,
      RESET             => RESET,
      Enable            => unsecondo and enable_cont_sec,
      Load_comando      => load or unminuto,
--   Load_valore        => conv_unsigned(59,6),
      Load_valore       => conv_unsigned(4,6),
      Valore            => cont_sec);
  
  unsecondo     <= '1' when cont_secondo = conv_unsigned(0,14) else '0';
  unminuto	<= '1' when cont_sec = conv_unsigned(0,6) and cont_secondo=conv_unsigned(0,14) else '0';
  fineminuti 	<= '1' when cont_min = conv_unsigned(0,5) and cont_sec = conv_unsigned(0,6) and cont_secondo=conv_unsigned(0,14) else '0';
  
  MIN   <= cont_min;
  SEC   <= cont_sec;
  
--- FSM
  process(CLK)
  begin
    if CLK'event and CLK='1' then
      if RESET ='1' then
        current_state   <= Idle;
      else
        current_state   <= next_state;
      end if;
    end if;
  end process;
  
--parte combinatoria
  process(START,GOAL,STOP,current_state,fineminuti,unminuto,end_sirena)
  begin
    
    enable_cont_sec     <= '0';
    load 	        <= '0';
    incrementa_tempo    <= '0';
    attiva_sirena 	<= '0';

    case current_state is
      
      when IDLE         =>
        next_state      <= carica;
	
      when CARICA       =>
        load            <= '1';
        if START='0' then
          next_state	<= current_state;
        else
          next_state	<= conta;
        end if;
	
      when CONTA        =>
        enable_cont_sec <= '1';
        if (STOP = '1' or GOAL ='1')  then
          next_state	<= ferma;
        elsif fineminuti = '1' and unminuto = '1'  then
          next_state 	<= sirena_attiva;
        else
          next_state    <= current_state;
        end if;

      when FERMA	=>
        if START = '0' then
          next_state	<= current_state;
        else
          next_state    <= CONTA;
        end if;

      -- seconda parte FSM
        
      when SIRENA_ATTIVA =>
        attiva_sirena   <= '1';
        if end_sirena = '1' then
          next_state    <= incrementa;
        else 
          next_state    <= current_state;
        end if;
      
      
      when INCREMENTA   =>
        incrementa_tempo<= '1';
        next_state      <= carica;
	
      when others 	=>
        next_state	<= idle; 
        
    end case;
  end process;

  --seconda parte CONTATORI
  
  process(CLK,RESET,incrementa_tempo)
  begin	
    if CLK'event and CLK='1' then
      if RESET='1' then
        current_conta_tempo<= conv_unsigned(1,2);
      elsif incrementa_tempo='1' then
        current_conta_tempo<= next_conta_tempo;
      end if;
    end if;
  end process;
  
  next_conta_tempo <= current_conta_tempo + conv_unsigned(1,2);
  
  process(CLK,RESET,attiva_sirena)
  begin
    if CLK'event and CLK='1' then
      if RESET='1' or load='1' then
        current_sirena<= conv_unsigned(0,13);
      elsif attiva_sirena='1' then
        current_sirena<= next_sirena;
      end if;
    end if;
  end process;
  
  next_sirena     <= current_sirena + conv_unsigned(1,13);
  end_sirena      <= '1' when current_sirena = conv_unsigned(5,13) else '0';
--end_sirena <= '1' when current_sirena = conv_unsigned(5000,13) else '0';
  
  TEMPO <= current_conta_tempo;
  SIRENA<= attiva_sirena;
  
end Esercizio;