library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity counter_nbit is
	generic (n: integer);
	port (
	CLK, RESET, ENABLE : in std_logic;
	conteggio : out unsigned(n downto 0)
	);
end counter_nbit;

architecture BEHAVIOR of counter_nbit is
signal next_value, value_temp: unsigned(n downto 0);

begin
		process(CLK) ---REGISTRO CON INGRESSO DI RESET e ENABLE
		begin
			if CLK'event and CLK='1' then
				if RESET='1' then
				value_temp<= (others => '0');
				elsif ENABLE = '1' then
				value_temp<= next_value;
				end if;
			end if;
		end process;
conteggio <= value_temp;
next_value<= value_temp+conv_unsigned(1,n+1);
end BEHAVIOR;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity reg_nbit is
generic (n: integer);
port (CLK, RESET, ENABLE: in std_logic;
	  D: in unsigned (n downto 0);
	  Q: out unsigned (n downto 0));
end reg_nbit;

architecture BEHAVIOR of reg_nbit is
begin
	process (CLK)
	 begin
		if CLK'event and CLK='1' then
			if RESET ='1' then 
			Q<= (others=>'0');
			elsif ENABLE ='1' then
			Q<= D;
			end if;
		end if;
	end process;
end BEHAVIOR;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

---numero di LE(Combinational ALUTs): 54/12480 (<1%)
---numero di LR(dedicated logic registers): 44/12480 (<1%)
---massima frequenza di funzionamento del circuito: 306.18 MHz
---dispositivo su cui è stata eseguita la sintesi: EP2S15F484C3 (Stratix II)

entity CONTROLLORE is
port( 
	CLK: in std_logic;
	RESET: in std_logic;
	ONOFF: in std_logic;
	FC_V: in unsigned(1 downto 0);
	FC_H: in unsigned(1 downto 0);
	ANGLE: in unsigned (7 downto 0);
	MOTOR_V: out unsigned(1 downto 0);
	MOTOR_H: out unsigned (1 downto 0);
	ATTIVA: out std_logic);
end CONTROLLORE;

architecture ESAME of CONTROLLORE is

type stato is (idle, stato1, stato2, stato3, stato4, ferma1, ferma2, ferma3, ferma4);
signal cs, ns: stato;
signal reset_cont, enable_cont, fine_disco, cinque_min: std_logic;
signal curr_angle, old_angle, diff_angle: unsigned (7 downto 0);
signal cont_int: unsigned (18 downto 0);

--registro a n bit
component reg_nbit
     generic (n: integer);
     port (CLK, RESET, ENABLE: in std_logic; 
			D: in unsigned (n downto 0);
			Q: out unsigned (n downto 0)
			);
end component;

--contatore a n bit
component counter_nbit 
	generic (n: integer);
	port (
	CLK, RESET, ENABLE : in std_logic;
	conteggio : out unsigned(n downto 0)
	);
end component;

begin

--Registro1 per la lettura di angle: l'ho inizializzato a 4, in modo che alla prima lettura non rilevi 
--subito la fine del disco; aggiorna curr_angle
process (CLK)
	 begin
		if CLK'event and CLK='1' then
			if RESET ='1' then 
			curr_angle<= conv_unsigned(4,8);
			elsif cinque_min ='1' then
			curr_angle<= ANGLE;
			end if;
		end if;
	end process;
	
--Registro2 per la lettura di angle: aggiorna old_angle
reg2: reg_nbit generic map (n=> 7)
				port map ( CLK=> CLK,
						   RESET=> RESET,
						   ENABLE=> cinque_min,
						   D=> curr_angle,
						   Q=> old_angle);
						   
diff_angle<= curr_angle-old_angle;

--processo che valuta se è stata o meno raggiunta la fine del disco
process (diff_angle, cinque_min)
begin
  if cinque_min='1' then
		if diff_angle<3 then 
			fine_disco<='1';
		else 
			fine_disco<='0';
		end if;
	else 
		fine_disco<='0';
  end if;
end process;

--contatore per i 5 minuti
contatore1: counter_nbit
				generic map (n=> 18)
				port map (
				CLK=> CLK,
				RESET=> reset_cont,
				ENABLE=> enable_cont,
				conteggio=> cont_int
				);
reset_cont<='1' when RESET='1' or cinque_min='1' else '0';
cinque_min<='1' when cont_int=conv_unsigned(4,19) else '0';--caso reale: conto fino a 299999


--parte sequenziale
process (CLK)
	begin
	if CLK'event and CLK='1' then
			if RESET='1' then
				cs<=idle;
			else cs<=ns;
			end if;
		end if;
	end process;

--parte combinatoria
process (cs, ONOFF, FC_V, FC_H, fine_disco)
begin
MOTOR_V<= conv_unsigned(0,2);
MOTOR_H<= conv_unsigned(0,2);
ATTIVA<= '0';
enable_cont<='0';
	case cs is
		when idle=> if ONOFF='1' then ns<= stato1;
					else ns<= cs;
					end if;
		when stato1=> MOTOR_V<= conv_unsigned(3,2);
				      if ONOFF='0' then ns<= ferma1;
					  else
						  if FC_V=conv_unsigned(1,2) then 
							ns<= stato2;
						  else 
							ns<= cs;
						  end if;
					  end if;
		when stato2=> MOTOR_H<= conv_unsigned(3,2);
					  if ONOFF='0' then ns<= ferma1;
					  else
						  if FC_H=conv_unsigned(1,2) then ns<= stato3;
						  else ns<= cs;
						  end if;
					  end if;
		when stato3=> MOTOR_V<=conv_unsigned(2,2);
					  if ONOFF='0' then ns<= ferma1;
					  else
							if FC_V=conv_unsigned(2,2) then ns<= stato4;
							else ns<= cs;
							end if;
					  end if;
	    when stato4=> ATTIVA<='1';
				      enable_cont<='1';
					  if ONOFF='0' or fine_disco='1' then ns<= ferma1;
					  else ns<= cs;
					  end if;
		when ferma1=> ATTIVA<='0';
					  ns<= ferma2;
		when ferma2=> MOTOR_V<=conv_unsigned(3,2);
						if FC_V=conv_unsigned(1,2) then ns<=ferma3;
						else ns<= cs;
					    end if;
		when ferma3=> MOTOR_H<=conv_unsigned(2,2);
						if FC_H=conv_unsigned(2,2) then ns<=ferma4;
						else ns<= cs;
					    end if;
		when ferma4=> MOTOR_V<=conv_unsigned(2,2);
						if FC_V=conv_unsigned(2,2) then ns<=idle;
						else ns<= cs;
					    end if;
		when others=> ns<=cs;
	end case;
end process;

end ESAME;