library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity controllore is
	port (
		CLK : in std_logic;
		RESET : in std_logic;
		--INTERFACCIA SENSORE
		READ_DATA : out std_logic;
		DATA : in unsigned(7 downto 0);
		--INTERFACCIA OTP
		OTP_ADDR : out std_logic;
		OTP_DATA : in unsigned(7 downto 0);
		--INTERFACCIA PANNELLO DI CONTROLLO
		READ_PRESSURE : in std_logic;
		SERIAL_DATA : out std_logic;
	    --pressure : out unsigned(8 downto 0);
		DATA_VALID : out std_logic);
		
end controllore;

architecture behavioural of controllore is

	type state is (idle, read_Offset, wait_offset, read_scale, wait_scale, read_sensor, wait_sensor, correction, transmission);
	signal current_state, next_state: state;
	signal register_offset : unsigned(7 downto 0);
	signal register_scale : unsigned(7 downto 0);
	signal register_data : unsigned(7 downto 0);
	signal pressure : unsigned(15 downto 0);
	signal next_cnt_10, current_cnt_10 : unsigned(11 downto 0);
	signal next_cnt_16, current_cnt_16 : unsigned(3 downto 0);
	signal wr, en_reg_off, en_reg_scale, en_reg_data : std_logic;
	signal end_cnt_10, start_cnt_10 : std_logic;
	signal end_cnt_16, start_cnt_16 : std_logic;
	
	begin
	
	-- Processo Combinatorio
	comb: process (current_state, read_pressure, OTP_DATA, end_cnt_10, end_cnt_16) is
		begin
		
			read_data <= '0';
			OTP_ADDR <= 'Z'; 
			data_valid <= '0';
			start_cnt_10 <= '0';
			start_cnt_16 <= '0';
			wr <= '0';
			en_reg_off <= '0';
			en_reg_scale <= '0';
			en_reg_data <= '0';
			
			case current_state is
				
				when idle =>
					if read_pressure = '1' then
						next_state <= read_Offset;
					else 
						next_state <= idle;
					end if;
				
				when read_Offset =>
					otp_addr <= '0';
					next_state <=wait_Offset;
					
				when wait_Offset =>
					en_reg_off <= '1';
					otp_addr <= '0';
					next_state <=read_Scale;
					
				when read_Scale =>
					otp_addr <= '1';
					next_state <= wait_Scale;
				
				when wait_Scale =>
					en_reg_scale <= '1';
					otp_addr <= '1';
					next_state <= read_sensor;
					
				when read_sensor =>
					read_data <= '1';
					next_state <= wait_sensor;
				
				when wait_sensor => 
					start_cnt_10 <= '1';
					if end_cnt_10 = '1' then
						next_state <= correction;
					else
						next_state <= wait_sensor;
					end if;
				
				when correction =>
					en_reg_data <= '1';
					wr <= '1';
					next_state <= transmission;
				
				when transmission =>
					start_cnt_16 <= '1';
					data_valid <= '1';
					if end_cnt_16 = '1' then
						next_state <= idle;
					else 
						next_state <= transmission;
					end if;
				
				when others => 
					next_state <= idle;
			
			end case;
	end process comb;

		
	--Contatore
	process (reset, clk) is
		begin
			if (reset = '1') then 
				current_cnt_10 <= conv_unsigned(0, 12);
			else 
				if (clk'event and clk = '1') then
					if (start_cnt_10 = '1') then
						current_cnt_10 <= next_cnt_10;
					end if;
				end if;
			end if;
	end process;
    
	end_cnt_10 <= '1' when current_cnt_10 = conv_unsigned(10,12) else '0';
	
	
	next_cnt_10 <= conv_unsigned(0,12) when end_cnt_10 = '1' else
				   current_cnt_10 + conv_unsigned(1,12);
				
	process (reset, clk) is
	begin
		if (reset = '1') then 
			current_cnt_16 <= conv_unsigned(0, 4);
		else
			if (clk'event and clk = '1') then
				if start_cnt_16 = '1' then
					current_cnt_16 <= next_cnt_16;
				end if;
			end if;
		end if;
	end process;
    
	end_cnt_16 <= '1' when current_cnt_16 = conv_unsigned(15,4) else '0';
	
	next_cnt_16 <= conv_unsigned(0,4) when end_cnt_16 = '1' else
				   current_cnt_16 + conv_unsigned(1,4);
	
	--Register offset
	process(clk, reset)
	begin
		if reset = '1' then 
			register_offset <= conv_unsigned(0,8);
		else
			if (clk'event and clk = '1') then
				if (en_reg_off = '1') then
					register_offset <= OTP_DATA; 
				end if;
			end if;
		end if;
	end process;
	
	--Register scale
	process(clk, reset)
		begin
		if reset = '1' then 
			register_scale <= conv_unsigned(0,8);
		else
			if (clk'event and clk = '1') then
				if (en_reg_scale = '1') then
					register_scale <= OTP_DATA; 
				end if;
			end if;
		end if;
	end process;	
	
	--Register data			 
	process(clk, reset, en_reg_data)
		begin
		if reset = '1' then 
			register_data <= conv_unsigned(0,8);
		else 
			if (clk'event and clk = '1') then
				if(en_reg_data = '1') then
					register_data <= DATA; 
				end if;
			end if;
		end if;
	end process;
	
	--Register pressure
	process(clk, reset, wr)
		begin
		if reset = '1' then
			pressure <= conv_unsigned(0,16);
		else 
			if (clk'event and clk = '1') then
				if (wr = '1') then
					pressure <= register_data*register_scale+register_offset;
				end if;
			end if;
		end if;	
	end process;
	
	-- Serial transmission
	process (clk, current_cnt_16,pressure) is
		begin
			case current_cnt_16 is
				when conv_unsigned(0,4) =>
					serial_data <= pressure(0);
				when conv_unsigned(1,4) =>
					serial_data <= pressure(1);
				when conv_unsigned(2,4) =>
					serial_data <= pressure(2);
				when conv_unsigned(3,4) =>
					serial_data <= pressure(3);
				when conv_unsigned(4,4) =>
					serial_data <= pressure(4);
				when conv_unsigned(5,4) =>
					serial_data <= pressure(5);
				when conv_unsigned(6,4) =>
					serial_data <= pressure(6);
				when conv_unsigned(7,4) =>
					serial_data <= pressure(7);
				when conv_unsigned(8,4) =>
					serial_data <= pressure(8);
				when conv_unsigned(9,4) =>
					serial_data <= pressure(9);
				when conv_unsigned(10,4) =>
					serial_data <= pressure(10);
				when conv_unsigned(11,4) =>
					serial_data <= pressure(11);
				when conv_unsigned(12,4) =>
					serial_data <= pressure(12);
				when conv_unsigned(13,4) =>
					serial_data <= pressure(13);
				when conv_unsigned(14,4) =>
					serial_data <= pressure(14);
				when conv_unsigned(15,4) =>
					serial_data <= pressure(15);
				when others =>
					serial_data <= '0';
			end case;
	end process;
	
	-- Processo Sequenziale
	process (reset, clk) is
			begin
				if reset = '1' then
					current_state <= idle;
				else
					if(clk'event and clk = '1') then
						current_state <= next_state;
					end if;
				end if;
	end process;

end architecture behavioural;