library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity sad4 is
port( clk,reset,enable        : in std_logic;
      curr0,curr1,curr2,curr3 : in unsigned(7 downto 0);
      ref0,ref1,ref2,ref3     : in unsigned(7 downto 0);
      output                  : out unsigned(10 downto 0) );
end sad4;

architecture struct of sad4 is

component reg
port( clk,reset,enable : in std_logic;
      data_in  : in  unsigned(7 downto 0);
      data_out : out unsigned(7 downto 0) );
end component;

component abs_diff is
port ( a,b : in unsigned(7 downto 0);
       c   : out unsigned(7 downto 0) );
end component;

signal temp0,temp1,temp2,temp3 : unsigned(7 downto 0);
signal ck_temp0,ck_temp1,ck_temp2,ck_temp3 : unsigned(7 downto 0);

begin

   ad0: abs_diff port map (curr0,ref0,temp0);   
   ad1: abs_diff port map (curr1,ref1,temp1);
   ad2: abs_diff port map (curr2,ref2,temp2);
   ad3: abs_diff port map (curr3,ref3,temp3);

   r0: reg port map (clk,reset,enable,temp0,ck_temp0);
   r1: reg port map (clk,reset,enable,temp1,ck_temp1);
   r2: reg port map (clk,reset,enable,temp2,ck_temp2);
   r3: reg port map (clk,reset,enable,temp3,ck_temp3);

   output <= ck_temp0+ck_temp1+ck_temp2+ck_temp3;
end struct;

----------------------------------------------------------

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity abs_diff is
port ( a,b : in unsigned(7 downto 0);
       c   : out unsigned(7 downto 0) );
end abs_diff;

architecture beh of abs_diff is
begin
  process(a,b)
  begin
    if (a>b) then 
       c <= (a-b);
    else
       c <= (b-a);
    end if;
  end process;
end beh;

-----------------------------------------------------------

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity reg is
port( clk,reset,enable : in std_logic;
      data_in  : in  signed(7 downto 0);
      data_out : out signed(7 downto 0) );
end reg;

architecture BEH of reg is
begin
   process(clk,reset)
   begin
     if reset='0' then 
        data_out <= (others => '0');
     else if clk'event and clk='1' then
             if enable='0' then
                data_out <= data_in;
             end if;
           end if;
     end if;
	end process;
end BEH;