library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity cognome is
port( clk,reset,enable : in std_logic;
      in_a,in_b        : in unsigned(7 downto 0);
      sel              : in std_logic_vector(1 downto 0);
      output : out unsigned(7 downto 0) );
end cognome;

architecture STRUCT of cognome is

type stato is (idle,a,b,c);
signal ns,cs       : stato;
signal res_a,res_b : unsigned(7 downto 0);

begin
  process(clk,reset)
  begin
    if reset = '0' then
       cs <= idle;  
    else 
      if clk'event and clk='0' then
         if enable='0' then 
            cs <= ns;
         end if;
      end if;
    end if;
  end process;

    res_a <= in_a + in_b;
    res_b <= in_a(5 downto 0)&"00";

    process(sel,cs,res_a,res_b)
    begin
      case cs is
        when idle =>  output <= (others => '0');
                      if sel="00" then 
							ns <= idle;
                      elsif sel="01" or sel="11" then 
							ns <= a;
					  elsif sel="10" then
							ns <= b;
					  else 
							ns <= idle;
					  end if;

         when a =>  output <= res_a;
                      if sel="00" or sel="01" then 
							ns <= a;
					  elsif sel="10" or sel="11" then
							ns <= b;
					  else 
							ns <= idle;
					  end if;

        when b =>  output <= res_b;
                      if sel="01" or sel="11"then 
							ns <= a;
					  elsif sel="00" or sel="10"  then
							ns <= b;
					  else 
							ns <= idle;
					  end if;

	    -- In caso di malfunzionamenti il sistema viene riportato 
        -- nello stato idle
		when others => output <= (others => '0');
					   ns <= idle;
	 end case;
   end process;

end STRUCT;