library IEEE;
   use IEEE.std_logic_1164.all;
   use IEEE.std_logic_arith.all;
   use IEEE.std_logic_unsigned.all;

entity XXX is
port ( clk,reset,enable     : in    std_logic;
       in_a,in_b,in_c       : in    unsigned(3 downto 0);
       output               : out   unsigned(8 downto 0) );
end XXX;

architecture STRUCT of XXX is

component reg
port ( clk,reset,enable : in std_logic;
       reg_in  : in  unsigned(3 downto 0);
       reg_out : out unsigned(3 downto 0) );
end component;

signal ck_a             : unsigned(3 downto 0);
signal temp1, ck_temp1  : unsigned(6 downto 0);
signal temp2, ck_temp2  : unsigned(5 downto 0);
signal temp3, ck_temp3  : unsigned(4 downto 0);

begin

  sample_a:reg port map(clk,reset,enable,in_a,ck_a);

   -- Non Pipelined: 
   -- Output <= (in_a * conv_unsigned(5,4) ) + (in_b * conv_unsigned(3,4)) + in_c  + ck_a; 

  -- Pipelined
  temp1 <= (in_a * conv_unsigned(5,4) );
  temp2 <= (in_b * conv_unsigned(3,4) );
  temp3 <= in_c  + ck_a;

  pipeline_registers: process(clk,reset,enable)
  begin
    if reset='0' then
       ck_temp1 <= conv_unsigned(0,7);
       ck_temp2 <= conv_unsigned(0,6);
       ck_temp3 <= conv_unsigned(0,5);
    else
       if clk'event and clk='1' then
          if enable='0' then
               ck_temp1 <= temp1;
               ck_temp2 <= temp2;
               ck_temp3 <= temp3;
          end if;
       end if;
    end if;
  end process;

  output <= ck_temp1+ck_temp2+ck_temp3;

end STRUCT;

-----------------------------------------------------------------------
-- DATA_REG : General purpose Register entity
-----------------------------------------------------------------------
library IEEE;
   use IEEE.std_logic_1164.all;
   use IEEE.std_logic_arith.all;
   use IEEE.std_logic_unsigned.all;
   
entity reg is
port ( clk,reset,enable : in std_logic;
       reg_in  : in  unsigned(3 downto 0);
       reg_out : out unsigned(3 downto 0) );
end reg;

architecture b of reg is
begin
  process(clk,reset)
  begin
    if reset='0' then
       reg_out <= ( others => '0');
    elsif clk'event and clk='1' then 
          if enable='0' then 
             reg_out <= reg_in;
          end if;
    end if; 
  end process;
end b;