library IEEE;
use IEEE.std_logic_1164.all;


entity HA is
port ( I1,I2 : in std_logic;
       SUM, CO : out std_logic);
end HA;

architecture BEHAVIOR of HA is
begin
   SUM <= (I1 xor I2);
   CO <= (I1 and I2);
end BEHAVIOR;

-----------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;


entity FA is
port ( A,B,CIN : in std_logic;
       S, COUT : out std_logic);
end FA;

-- architecture BEHAVIOR of FA is
-- begin
--    S <= (A xor B) xor CIN;
--    COUT <= (A and B) or (B and CIN) or (A and CIN);
-- end BEHAVIOR;

architecture STRUCTURAL of FA is
   component HA
   port ( I1,I2   : in std_logic;
          SUM, CO : out std_logic);
   end component;
signal S1, C1, C2 : std_logic;
begin
   ha1 : HA port map( I1 => B, I2 => CIN, SUM => S1, CO => C1);
   ha2 : HA port map( I1 => A, I2 => S1, SUM => S, CO => C2);

   COUT <= C2 xor C1;
end STRUCTURAL;


-----------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;

entity ADDER is
port ( A, B : in  std_logic_vector(3 downto 0);
       CIN  : in  std_logic;
	   COUT : out std_logic;
       S    : out std_logic_vector(3 downto 0) );
end ADDER;

architecture STRUCTURAL of ADDER is
   component FA
   port ( A,B,CIN : in std_logic;
          S, COUT : out std_logic);
   end component;
signal K : std_logic_vector(4 downto 0);
begin

    adder_loop : for I in 0 to 3 generate
       fa_I : FA port map ( A => A(I), B => B(I), CIN => K(I), COUT => K(I+1), S => S(I) );
    end generate;

    K(0) <= CIN;
    COUT <= K(4);

end STRUCTURAL;

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