library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity  condivisa is
Port ( clk,reset,enable : in std_logic;
       Cycles           : in unsigned(4 downto 0);
       Cycles_sample    : in std_logic;
       En_a,en_b,en_c   : out std_logic );
end  condivisa;

architecture beh of condivisa is

type state is (zero,A,B,C);
signal count,ncount,ck_cycles : unsigned(4 downto 0);
signal cs,ns : state;

begin

Cycles_sampling: process(clk,reset)
begin
  if reset='1' then ck_cycles <= (others => '0');
  else if clk'event and clk='1' then
             if enable='1' and cycles_sample='1' then 
                ck_cycles <= cycles;
             end if;
       end if;
  end if;
end process;

count_update: process(clk,reset)
begin
  if reset='1' then count <= conv_unsigned(0,5);
  else  if clk'event and clk='1' then
           if enable='1' then 
              count <= ncount;
           end if;
        end if;
  end if;
end process;

FSM_update: process(clk,reset)
begin
  if reset='1' then cs <= zero;
  else  if clk'event and clk='1' then
           if enable='1' then 
              cs <= ns;
           end if;
        end if;
  end if;
end process;

FSM: process(cs,count,ck_cycles)
begin
  case cs is
     when zero => en_a <= '1';
                  en_b <= '1';
                  en_c <= '1';
                  if ck_cycles = conv_unsigned(0,5) then
                     ns <= zero;
                     ncount <= conv_unsigned(0,5);
                  else 
                     ns <= A;
                     ncount <= ck_cycles;
                  end if;
                  
     when A => en_a <= '0';
               en_b <= '1';
               en_c <= '1';
               
               if ck_cycles = conv_unsigned(0,5) then
                     ns <= zero;
                     ncount <= conv_unsigned(0,5);
                     
               elsif count = conv_unsigned(0,5) then
                     ns <= B;
                     ncount <= ck_cycles;
               else
                     ns <= A;
                     ncount <= count - conv_unsigned(1,5);                  
               end if;
  
     when B => en_a <= '1';
               en_b <= '0';
               en_c <= '1';
               
               if ck_cycles = conv_unsigned(0,5) then
                     ns <= zero;
                     ncount <= conv_unsigned(0,5);
                     
               elsif count = conv_unsigned(0,5) then
                     ns <= C;
                     ncount <= ck_cycles;
               else
                     ns <= B;
                     ncount <= count - conv_unsigned(1,5);                  
               end if;

     when C => en_a <= '1';
               en_b <= '1';
               en_c <= '0';
               
               if ck_cycles = conv_unsigned(0,5) then
                     ns <= zero;
                     ncount <= conv_unsigned(0,5);
                     
               elsif count = conv_unsigned(0,5) then
                     ns <= A;
                     ncount <= ck_cycles;
               else
                     ns <= C;
                     ncount <= count - conv_unsigned(1,5);                  
               end if;
   end case;
end process;
               
end beh;