library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

-- La soluzione proposta descrive il caso pipelined, ma il funzionamento sarebbe combinatorio 
-- eliminando i processi REG1, REG2

entity SAD is
port ( clk,reset       : in  std_logic;
       a,b,c,d         : in  signed(5 downto 0);
       sad_out         : out signed(7 downto 0) );
end SAD;

architecture small of sad is
signal dif1,dif2,add1,add2,ck_add1,ck_add2,ck_dif1,ck_dif2 : signed(6 downto 0);

begin
  
  dif1 <= a-b;
  dif2 <= c-d;

REG1: process(clk,reset)
  begin
    if reset='1' then
          ck_dif1 <= (others=>'0');
          ck_dif2 <= (others=>'0');
    else if clk'event and clk='1' then
             ck_dif1 <= dif1;
             ck_dif2 <= dif2;
         end if;
    end if;
  end process;


  process(ck_dif1)
  begin
    if ck_dif1(6)='0' then 
       add1 <= ck_dif1;
    else 
       add1 <= conv_signed(0,7) - ck_dif1;
    end if;
  end process;

  process(ck_dif2)
  begin
    if ck_dif2(6)='0' then 
       add2 <= ck_dif2;
    else 
       add2 <= conv_signed(0,7) - ck_dif2;
    end if;
  end process;

REG2: process(clk,reset)
  begin
    if reset='1' then
          ck_add1 <= (others=>'0');
          ck_add2 <= (others=>'0');
    else if clk'event and clk='1' then
             ck_add1 <= add1;
             ck_add2 <= add2;
         end if;
    end if;
  end process;

  sad_out <= ck_add1+ck_add2;

end small;