library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity PARITY is port ( clk,reset : in std_logic; data_in : in unsigned(8 downto 0); buff_full : in std_logic; addr_out : out unsigned(5 downto 0); data_out : out unsigned(15 downto 0); fail : out std_logic ); end PARITY; architecture beh of parity is type stati is (leggi1,leggi2,err); signal cs,ns : stati; signal count,ncount : unsigned(5 downto 0); signal par : std_logic; signal word,nword : unsigned(15 downto 0); begin par <= data_in(7) xor data_in(6) xor data_in(5) xor data_in(4) xor data_in(3) xor data_in(2) xor data_in(1) xor data_in(0); -- Aggiornamento dello stato process(clk,reset) begin if reset='1' then cs <= leggi1; count <= conv_unsigned(0,6); word <= conv_unsigned(0,16); else if clk'event and clk='1' then cs <= ns; count <= ncount; word <= nword; end if; end if; end process; process(clk,reset) begin if reset='1' then data_out <= (others=>'0'); else if clk'event and clk='1' then if cs=leggi2 then data_out <= nword; end if; end if; end if; end process; process(cs,word,buff_full,data_in,par) begin case cs is when leggi1 => addr_out <= count; fail<='0'; if buff_full='1' or par /= data_in(8) then ns<=err; else ns<=leggi2; end if; nword(7 downto 0) <= data_in(7 downto 0); nword(15 downto 8) <= word(15 downto 8); ncount <= count; when leggi2 => addr_out <= count; fail<='0'; if buff_full='1' or par /= data_in(8) then ns<=err; else ns<=leggi1; end if; nword(7 downto 0) <= word(7 downto 0); nword(15 downto 8) <= data_in(7 downto 0); ncount <= count+conv_unsigned(1,6); when err => fail<='1'; ns <= err; addr_out <= ( others => '0'); nword <= (others => '0'); ncount <= conv_unsigned(0,6); end case; end process; end beh;