library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_signed.all; entity mac_compl is port ( clk,res,en : in std_logic; Ar : in signed(4 downto 0); Ai : in signed(4 downto 0); Br : in signed(4 downto 0); Bi : in signed(4 downto 0); Yr : out signed(10 downto 0); Yi : out signed(10 downto 0) ); end mac_compl; architecture bb of mac_compl is component reg port ( clk,reset,enable : in std_logic; reg_in : in signed(10 downto 0); reg_out : out signed(10 downto 0) ); end component; component mul_compl port ( clk,res,en : in std_logic; Ar : in signed(4 downto 0); Ai : in signed(4 downto 0); Br : in signed(4 downto 0); Bi : in signed(4 downto 0); Yr : out signed(10 downto 0); Yi : out signed(10 downto 0) ); end component; signal temp_r,temp_i,acc_r,acc_i, ck_acc_r,ck_acc_i : signed(10 downto 0); begin moltiplicatore: mul_compl port map (clk,res,en,Ar,Ai,Br,Bi,temp_r,temp_i); acc_r <= ck_acc_r + temp_r; acc_i <= ck_acc_i + temp_i; reg_acc_r: reg port map (clk,res,en,acc_r,ck_acc_r); reg_acc_i: reg port map (clk,res,en,acc_i,ck_acc_i); Yr <= ck_acc_r; Yi <= ck_acc_i; end bb; --- MOLTIPLICATORE COMPLESSO A PIPELINE !!! ------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_signed.all; entity mul_compl is port ( clk,res,en : in std_logic; Ar : in signed(4 downto 0); Ai : in signed(4 downto 0); Br : in signed(4 downto 0); Bi : in signed(4 downto 0); Yr : out signed(10 downto 0); Yi : out signed(10 downto 0) ); end mul_compl; architecture aa of mul_compl is signal ck_Ar,ck_Br,ck_Ai,ck_Bi : signed(4 downto 0); signal r1,r2,i1,i2, ck_r1,ck_r2,ck_i1,ck_i2 : signed(9 downto 0); signal outr,outi,ck_outr,ck_outi : signed(10 downto 0); begin -- Parte sequenziale process(clk,res) begin if res='1' then -- Campionamento di ingressi e uscite (facoltativo) ck_Ar <= ( others => '0'); ck_Br <= ( others => '0'); ck_Ai <= ( others => '0'); ck_Bi <= ( others => '0'); ck_outr <= ( others => '0'); ck_outi <= ( others => '0'); ck_r1 <= ( others => '0'); ck_r2 <= ( others => '0'); ck_i1 <= ( others => '0'); ck_i2 <= ( others => '0'); elsif clk'event and clk='1' then if en='1' then -- Campionamento di ingressi e uscite (facoltativo) ck_Ar <= Ar; ck_Br <= Br; ck_Ai <= Ai; ck_Bi <= Bi; ck_outr <= outr; ck_outi <= outi; ck_r1 <= r1; ck_r2 <= r2; ck_i1 <= i1; ck_i2 <= i2; end if; end if; end process; -- Elaborazioni degli operandi parziali r1 <= ck_Ar * ck_Br; r2 <= ck_Ai * ck_Bi; i1 <= ck_Ar * ck_Bi; i2 <= ck_Br * ck_Ai; -- calcolo dei due termini del prodotto outr <= ck_r1-ck_r2; outi <= ck_i1+ck_i2; -- sincronizzazione delle uscite Yr <= ck_outr; Yi <= ck_outi; end aa; --- Solito Registro con reset asincrono library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_signed.all; entity reg is port ( clk,reset,enable : in std_logic; reg_in : in signed(10 downto 0); reg_out : out signed(10 downto 0) ); end reg; architecture b of reg is begin process(clk,reset) begin if reset='1' then reg_out <= ( others => '0'); elsif clk'event and clk='1' then if enable='1' then reg_out <= reg_in; end if; end if; end process; end b; ---------------------------------------------------------------------