---------------------------------------------------------------------
--     fir_da.vhd
-- Soluzione del Tema di Esame del 11 giugno 2002
-- (Architetture di Sistemi Integrati/ Progetto di sistemi elettronici)
---------------------------------------------------------------------

-- NOTA: Questa soluzione e' stata mappata su dispositivo
-- MAX7000 EMP7064LC44-7
-- Frequenza max 21.2 MHZ
-- Logic cells 39    FFs 8 (12 utilizzando Reg0)

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity fir_da is
port (clk,reset,enable : in  std_logic;
      in_chan          : in  unsigned(3 downto 0);
      out_chan         : out unsigned(7 downto 0) );
end fir_da;

architecture s of fir_da is

component lut
port ( addr_in   : in  std_logic_vector(2 downto 0);
       data_out  : out unsigned(3 downto 0) );
end component;

component reg
port ( clk,reset,enable : in std_logic;
       reg_in  : in  unsigned(3 downto 0);
       reg_out : out unsigned(3 downto 0) );
end component;

signal x0,x1,x2 : unsigned(3 downto 0);
signal x0s,x1s,x2s : std_logic_vector(3 downto 0);
signal in_lut0,in_lut1,in_lut2,in_lut3 : std_logic_vector(2 downto 0);
signal out_lut0,out_lut1,out_lut2,out_lut3 : unsigned(3 downto 0); 
signal adderin0,adderin1,adderin2,adderin3 : unsigned(7 downto 0);

begin

  -- Nota: la presenza di questo registro sincronizza l'ingresso, cosicche'
  -- in realta' ad ogni ingresso x(n) compare l'uscita y(n-1).
  -- E' usato(facoltativamente) per evitare glitches.
  reg0 : reg port map (clk,reset,enable,in_chan,x0);

  reg1 : reg port map (clk,reset,enable,x0,x1);
  reg2 : reg port map (clk,reset,enable,x1,x2);

  x0s <= conv_std_logic_vector(x0,4);
  x1s <= conv_std_logic_vector(x1,4);
  x2s <= conv_std_logic_vector(x2,4);

  in_lut0 <= x0(0)&x1(0)&x2(0);
  in_lut1 <= x0(1)&x1(1)&x2(1);
  in_lut2 <= x0(2)&x1(2)&x2(2);
  in_lut3 <= x0(3)&x1(3)&x2(3);

  lut0 : lut port map (in_lut0,out_lut0);
  lut1 : lut port map (in_lut1,out_lut1);
  lut2 : lut port map (in_lut2,out_lut2);
  lut3 : lut port map (in_lut3,out_lut3);

  adderin0 <= "0000"&out_lut0;
  adderin1 <= "000"&out_lut1&'0';
  adderin2 <= "00"&out_lut2&"00";
  adderin3 <= '0'&out_lut3&"000";

  out_chan <= adderin0 + adderin1 + adderin2 + adderin3;

end s;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity lut is
port ( addr_in   : in  std_logic_vector(2 downto 0);
       data_out  : out unsigned(3 downto 0) );
end lut;

architecture b of lut is
constant a0 : positive := 1;
constant a1 : positive := 2;
constant a2 : positive := 1;
begin
  process(addr_in)
  begin
    if addr_in=conv_std_logic_vector(0,3) then 
         data_out <= conv_unsigned(0,4);
    elsif addr_in=conv_std_logic_vector(1,3) then 
         data_out <= conv_unsigned(A0,4);
    elsif addr_in=conv_std_logic_vector(2,3) then 
         data_out <= conv_unsigned(A1,4);
    elsif addr_in=conv_std_logic_vector(3,3) then 
         data_out <= conv_unsigned(A1+A0,4);
    elsif addr_in=conv_std_logic_vector(4,3) then 
         data_out <= conv_unsigned(A2,4);
    elsif addr_in=conv_std_logic_vector(5,3) then 
         data_out <= conv_unsigned(A2+A0,4);
    elsif addr_in=conv_std_logic_vector(6,3) then 
         data_out <= conv_unsigned(A2+A1,4);
    elsif addr_in=conv_std_logic_vector(7,3) then 
         data_out <= conv_unsigned(A2+A1+A0,4);
    else 
         data_out <= conv_unsigned(0,4); 
    end if;
  end process;
end b;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity reg is
port ( clk,reset,enable : in std_logic;
       reg_in  : in  unsigned(3 downto 0);
       reg_out : out unsigned(3 downto 0) );
end reg;

architecture b of reg is
begin
  process(clk,reset)
  begin
    if reset='1' then
       reg_out <= ( others => '0');
    elsif clk'event and clk='1' then 
          if enable='1' then reg_out <= reg_in;
          end if;
    end if; 
  end process;
end b;