Methodologies for rapid design, validation and emulation of
integrated digital systems
The aim of this research activity is the study and the development of
methodologies for the design, validation and emulation of integrated
digital systems emphasizing the quick turn-around time. This activity
is mainly divided into two parts: the design of application specific
integrated circuits (ASICs) and the design of the complex boards
in which they will be included.
In the first part of the activity efferent methodology approaches are
used, all based upon high level description languages (VHDL,
CHDL, Verilog) which support different technologies such as
standard-cells, sea-of-gates, FPGA. Using a standard-cells
technology a chip-set for a parallel architecture dedicated to
classification problems using the k-Nearest-Neighbor algorithm (
KNN) has been implemented. A framework for an aided design of
sea-of-gates integrated circuits is also under development, with which
three devices for image processing conforming to the H.261 CCITT
standard has been fabricated. FPGA are used only for the
emulation and rapid development of prototypes.
As the second part of the activity prototyping boards based on
programmable interconnecting matrixes are being studied as a tool for
validating both system and ASICs under development. A key factor is
the study and development of a framework for software simulation and
hardware emulation allowing the validation of systems made up of both
hardware parts and virtual ones whose behavior is described using a
hardware high level description language. Using this technique two
boards have been developed, one for OCR applications based on the
chip-set described above, and another one for the acquisition, coding
and transmission of images according to the H.261 CCITT standard.