A feature-extraction chip for speech recognition computes fifteen cepstra each 8ms at 64kHz clock rate and dissipates 30uW at 0.9V. It has been implemented as a gate array in a 0.5um, three-metal CMOS technology. The average energy required to process a single word of the TI46 speech corpora is 10uJ. It achieves recognition rates over 98% in isolated-word, speech recognition tasks. The main contribution of this paper is the description of the implementation of an integrated circuit that implements a novel, highly simplified algorithm achieving efficient speech feature computation and compression, and very low-power and low-voltage operation.
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