This article presents a novel approach to the high-level system verification problem based on a hybrid hardware/software virtual emulation tool. Unavailable components or sub-systems are physically replaced on a prototype board by FPGAs whose electrical behavior is driven by software simulations of high-level description models. Such a prototype can smoothly evolve towards the final system as soon as the unavailable parts or the components under manufacturing become available. The simultaneous use of prototyping techniques such as field-programmable circuit boards with software simulation significantly improve the usefulness of our framework. A low-cost verification environment, with multiprocessing and multilanguage capabilities currently in use at University of Bologna, is described.

Microelectronics Group Home Page	Staff
Research Activities	Teaching Activity
Publications	Local Stuff
DEIS Home Page	University of Bologna Home Page