University of Bologna

Dipartimento di Elettronica, Informatica e Sistemistica

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Searched for "ESSCIRC2001:Cam"
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IP-Reusable 32-Bit VLIW Risc Core

F. Campi and R. Canegallo and R. Guerrieri


This paper presents a 32-Bit, Very Long Instruction Word RISC microcontroller specifically designed for IP-Reuse in a system-on-chip design context. The architecture aims at minimizing instruction cycles for a wide range of software applications: a 32-bit instruction set is defined for normal execution, while a reduced 16-bit instruction set allows the microprocessor to fetch instruction pairs for concurrent double-datapath execution. The architecture is described through a parametric, fully synthesizable VHDL RTL model targeted at both FPGA and Standard Cells design, and is supported by a complete software development suite derived from the open-source GNU-Gcc toolchain. The model has been synthesized to 0.18um 6-metal Std-cells technology, functioning at 120 MHZ with an area occupation of 2.72 mm^2 (30K cells, 90K gates). A test chip for the architecture has also been manufactured in 0.18um technology, featuring 128K bytes of Data as well as 128K bytes of Instruction Memory, for an area occupation of 3.2mm^2 at 66 MHZ with 1.8V power supply.

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